In U.S. Pat. No. 5,043,820, issued on Aug. 27, 1991, entitled “Focal plane array readout employing one capacitive feedback transimpedance amplifier for each column”, Wyles et al. disclose a readout circuit for use with a focal plane array that employs a single transistor in each unit cell and a single capacitive feedback transimpedance amplifier (CTIA) to process the outputs of each column of detector elements of the array. The capacitive feedback transimpedance amplifiers extract the signals associated with the pixels along a particular row of the array. The disclosed invention permits high performance readouts to be constructed with little circuitry in the unit cells. For example, only a single minimum sized transistor switch is required in each unit cell to perform readout and reset functions for the array.
Referring to FIGS. 1 and 2, in a disclosed embodiment the readout circuit includes an array of unit cells 1, where each unit cell 1 includes a detector input circuit 1A, a transistor (TR) and a single charge storage capacitor (CAP). Row address circuits 2 are coupled to the cells in each row of the array 1, and a plurality of capacitive feedback transimpedance amplifiers 3 are coupled to the cells in each column of the array. The amplifiers process charge derived from the detector elements and stored in the charge storage capacitor (CAP) of each unit cell 1. Column multiplexing circuits multiplex the output signals provided by each of the amplifiers. Column address circuits 4 are coupled to the column multiplexing circuits which couple output signals from each of the multiplexer circuits as the output from the readout circuit.
The charge mode readout made possible by using the circuit shown in FIG. 1 is achieved by using a CTIA at each column output. The CTIA operates to hold the vertical busline connecting a column of unit cells 1 at a virtual ground, while extracting the charge from the unit cell integration capacitors. The charge mode output, direct injection input circuit generally provides the largest integration storage capacity in the smallest unit cell circuit area. General reference with regard to CTIAs can be made, as examples, to U.S. Pat. No. 4,978,872, “Integrating Capacitively Coupled Transimpedance Amplifier”, Morse, Gaalema, Keimel and Hewitt, and to U.S. Pat. No. 6,121,843, “Charge Mode Capacitor Transimpedance Amplifier”, Vampola and Hewitt.
While well suited for use in many important applications, it has been found that the unit cell design illustrated in FIG. 1 does not lend itself to implementing a true “snapshot integrate-while-read” capability. The use of snapshot integration is desirable for operation in highly dynamic imaging systems to prevent the creation of image artifacts that can be generated by non-simultaneous scene-derived charge integration, sometimes referred to as “rolling frame integration”.
This problem is related to a problem that can be experienced by IR sensors that operate in an IRST (IR Search and Track) mode of operation. In the IRST mode the sensors must accommodate a large dynamic range. A typical response to the wide dynamic range requirement is to obtain two signal samples that are closely-spaced in time with different integration or exposure times, e.g., a low gain sample with a short integration time and a high gain sample with a long integration time. In the conventional circuit having a single integration well per detector input, as in FIG. 1, the two integration times are separated by a full readout frame time (e.g., tens of milliseconds when operating with a 30 Hz frame rate). As can be appreciated, when the scene radiation is rapidly changing this amount of delay can be objectionable, and may result in ambiguous scene data being generated.
In an attempt to provide a snapshot integrate-while-read capability with the conventional unit cell circuitry it has been known to add a sample/hold capacitor to each unit cell. While allowing snapshot integration, this approach also attenuates the input signal, and reduces the amount of charge that can be accumulated. Also, since charge division occurs between the integration capacitor and the sample/hold capacitor, a non-uniformity in the ratio of these two capacitors can result in an undesirable variation in gain over the two-dimensional array of unit cells.